HDL & ASIC Related sites

IEEE Working Groups

• Open Model Forum (OMF)
• VHDL Initiative Towards ASIC Libraries (VITAL)
• 1029.1 Standard for VHDL Waveform and Vector Exchange (WAVES)
• 1076.1 Analog and Mixed-Signal Extensions to VHDL
• 1076.3 VHDL Synthesis
• 1076.5 VHDL LibUtil
• 1364 Verilog Standardization *
• 1481 Delay and Power Calculation

IEEE Study Groups

• VHDL Hardware Software Codesign
• VHDL Synthesis Interoperability
• Object-Oriented VHDL

Tutorials/Guides

• Hardware Designer’s Guide to Verilog
• Hardware Engineers Guide to VHDL
• Introduction to VHDL
• Introductory VHDL Tutorial
• Verilog/HDL ASIC Design Guidelines
• VHDL Cookbook
• VHDL Examples for Synthesis
• VHDL Methodology for FPGAs
• VHDL Synthesis Tutorials
• Vital Tutorial

Other HDL Related Sites

• Designer's Guide to VHDL (book advertisement)
• Doulos' Model of the Month
• Doulos' Tip of the Month
• Free Model Foundation
• Hamburg VHDL Archive
• High Level Synthesis Design Repository (FTP site)
• Microsystems Prototyping Laboratory's Model Repository
• Verilog & EDA Information
• Verilog FAQ (alternate)
• Verilog Internet Services *
• VHDL FAQ
• VHDL for Programmable Logic (book advertisement)
• VHDL International
• VHDL Internet Services
• VHDL International Users' Forum
• VHDL Made Easy (book advertisement)
• VHDL Reference Page
• VHDL UK
• Check the Conferences/Symposiums page for
  HDL related conferences/symposiums.
• MRC Institute Home Page

Other sites with useful information.....

EDA tool vendors

Wellspring Solutions (Makers of a Free 1000 line simulator)

Synopsys Corporation

X-Tek Corporation (VHDL to Verilog Translator)

InterHDL (VHDL2verilog, verilint, viper)

Alternative System Concepts (VHDL2verilog, ASIC test, etc...)

Advice, FAQs, archives, etc...

The comp.lang.vhdl FAQ

The comp.lang.verilog FAQ

The Verilog archive at Silicon Logic

The Alternate comp.lang.verilog FAQ

Rajesh Bawankule's Verilog Page (This has some GREAT info!)

University of Idaho's Links to VLSI Information

Willamette HDL Cool Verilog Stuff

Programmable Logic Jump Station

Guidelines on managing your verilog design

Verilog Reference Material by Gerard M Blair

Verilog Intro - postscript

Verilog and Synthesis Books

HDL Chip Design by Douglas Smith

Verilog HDL:Design and Synthesis by Samir Palnitkar

Asic Flow complete Asic

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